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加载电路
loaded circuit
- 该数据加载和读取电路生成地址信号。
Address signals are generated by the data loading and reading circuitry. - 数据加载和读取电路向存储器单元中加载数据并从存储器单元 读取数据。
Data loading and reading circuitry loads data into the memory elements and reads data from the memory elements. - FPGA设计可以自由地加以改变、重新编译和重新加载到电路板上，由此而来的责任是记录变更和保持FPGA设计的版本在配置控制之下。
With the freedom to change, recompile and reload the FPGA design to a board comes the responsibility to keep track of changes and keep FPGA design versions under configuration control.
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