控制总线信号 control bus signal
- 这节描述过去常为总线控制仲裁的信号。这些信号是新EISA信号和存在ISA信号的联合。
This section describes signals used to arbitrate for bus control. These signals are a combination of new EISA signals and existing ISA signals. - 当CPU访问到外部的存储器是,仿真模型将会驱动地址、数据和控制总线产生正确的信号,而外部的译码电路和存储器模型将会与之呼应对正确的存储器位置进行读写操作。
When the CPU accesses external memory, the model will drive the address, data and control lines appropriately, and external decode logic and memory model will respond by reading or writing the appropriate locations. - 地址总线和联系信号被控制主人使用维护存储器地址或I/O地址(M/-IO),以使一个奴隶能拴住地址和地位信号(-S0,-S1),并且显示存储器地址比16MB大。
The address bus and the associated signals are used by the controlling master to assert the memory address or the I/O address ( M/-IO ), to enable a slave to latch the address and status signals ( -S0, -S1 ), and to indicate that the memory address is greater than 16MB.
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